Trench isolation using gated sidewalls

A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

• a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;
• b) forming a conformal oxide layer to the sidewalls and bottom of said trench;
• c) removing said conformal oxide layer from said bottom of said trench;
• d) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;
• e) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;
• f) removing said exposed portions of the conductively doped polysilicon layer;
• g) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;
• h) forming a sacrificial oxide layer over said exposed starting silicon substrate portions and said conductively doped polysilicon layer's exposed upper ends;
• i) conductively doping said starting silicon substrate;
• j) removing said sacrificial oxide layer;
• and
• k) forming a gate oxide layer over said starting silicon substrate for said active devices.

A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting substrate, said process comprising:

• a) forming trenches into said starting substrate, said starting substrate being masked with patterned insulating layers;
• b) forming a conformal insulating layer to the sidewalls and bottom of said trench;
• c) forming a conductive material layer over the sidewalls and bottom of said trench;
• d) forming a planarized insulating layer inside said trench while exposing portions of said conductive layer;
• e) removing said exposed portions of the conductive layer;
• f) removing said patterned insulating layers thereby exposing portions of said starting substrate and exposing the upper ends of said conductive layer;
• g) forming a sacrificial insulating layer over said exposed substrate portions and said conductive layer's exposed upper ends;
• h) conductively doping said starting substrate;
• i) removing said sacrificial insulating layer;
• and
• j) forming a gate insulating layer over said starting substrate for said active devices.

A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting substrate, said process comprising:

• a) forming trenches into said starting substrate, said starting substrate being masked with patterned insulating layers;
• b) forming a conformal insulating layer to the sidewalls and bottom of said trench;
• c) forming a conductive material layer over the sidewalls and bottom of said trench;
• d) forming a planarized insulating layer inside said trench while exposing portions of said conductive layer;
• e) removing said exposed portions of the conductive layer;
• f) removing said patterned insulating layers thereby exposing portions of said starting substrate and exposing the upper ends of said conductive layer;
• g) conductively doping said starting substrate.

A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

• a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;
• b) forming a conformal oxide layer to the sidewalls and bottom of said trench;
• c) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;
• d) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;
• e) removing said exposed portions of the conductively doped polysilicon layer;
• f) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;
• g) forming a sacrificial oxide layer over said exposed starting silicon substrate portions and said conductively doped polysilicon layer's exposed upper ends;
• h) conductively doping said starting silicon substrate;
• i) removing said sacrificial oxide layer;
• and
• j) forming a gate oxide layer over said starting silicon substrate for said active devices.

A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

• a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;
• b) forming a conformal oxide layer to the sidewalls and bottom of said trench;
• c) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;
• d) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;
• e) removing said exposed portions of the conductively doped polysilicon layer;
• f) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;
• g) conductively doping said starting silicon substrate.