Process for filling submicron spaces with dielectric
AssigneeIntel Corporation
InventorsEbrahim Andideh, Robert J. Patterson
Life of this patent
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Abstract
A process for filling submicron, high aspect ratio gaps, that may have reentrant angles, with a high quality ILD. A first ILD layer is deposited using PECVD to partially fill the gap. Medium-pressure sputter etching is then used to remove the bread-loaf edges and redeposit the etched material in the gaps, thereby allowing small gaps with high aspect ratios and reentrant angles to be completely filled. Finally, a second ILD layer that completely fills the gap is deposited using PECVD.
Claims19
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of:
- depositing a first ILD layer using chemical vapor deposition, CVD, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles;
- sputter etching said first ILD layer, said sputter etching being performed at a pressure such that a substantial amount of the etched ILD material is redeposited in said gaps, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of:
- depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles;
- sputter etching said first ILD layer, said sputter etching being performed at a pressure such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of:
- depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of:
- depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD, with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of:
- depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of:
- depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of:
- depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of:
- depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle;
- sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step;
- and
- depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.
Dependencies are inferred from the claim text.