US 5,268,330 A · Process for improving sheet resistance of an integrated circuit device gate

Abstract

A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.

Claims37

Dependent claims

A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each said junction, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising:

depositing a passivating layer on said integrated circuit structure;
depositing an insulating layer on said passivating layer;
planarizing said insulating layer;
planarly removing said planarized insulating layer to expose said passivating layer above said gate;
removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate;
creating a trench in said insulating layer above at least one junction selective to said passivating layer;
extending said trench through said passivating layer selective to said at least one junction;
forming a first contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material;
and
forming a second contact by planarly filling said extending trench above said at least one junction with a second low sheet resistance conductive material.

7 more elements

A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each of said junctions, an isolation region in said substrate next to at least one of said junctions, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising:

depositing a passivating layer on said integrated circuit structure;
depositing an insulating layer on said passivating layer;
planarizing said insulating layer;
planarly removing said planarized insulating layer to exposed said passivating layer above said gate;
removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate;
forming a trench in said insulating layer above said at least one junction selective to said passivating layer, said trench being partially above at least one junction and partially above said isolation region;
extending said trench through said passivating layer selective to said at least one junction and said isolation region;
forming a contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material;
and
forming a borderless contact by planarly filling said extended trench with a second low sheet resistance conductive material.

7 more elements

Dependencies are inferred from the claim text.

Process for improving sheet resistance of an integrated circuit device gate

Life of this patent

Process for improving sheet resistance of an integrated circuit device gate

Life of this patent

Abstract

Claims37