High performance architecture for image processing

A logical computer architecture for image and signal processing, and other related computations, using a data flow concept for performing operations of an image algebra having an algebraic set of operators;

• wherein the architecture comprises three tightly coupled processing components:
• a spatial configuration processor (process S), a weighting processor using a point-wise operation (process W), and an accumulation processor (process A), wherein the data flow and image processing operations are directed by a control buffer and pipelined to each of said three processing components;
• wherein the spatial configuration processor has an input for an original image and an input for a template, and in operation uses a step-wise discrete convolution of the original input image with each template location, with a unit value assigned to a template element for each convolution, a result of each convolution being a shift of an input image element, providing an output of the spatial configuration processor which is coupled to the weighting processor;
• wherein the output of the spatial configuration processor is combined point-wise in the weighting processor, using an appropriate binary associative operator from the algebraic set of operators, with the value of the respective template element, the operation of the weighting processor being an array process execution using said appropriate binary associative operator, the weighting processor having an output coupled to the accumulation processor;
• wherein the output of the weighting processor is accumulated point-wise in the accumulation processor, using an appropriate global reduce operator from the algebraic set of operators, the accumulation processor having an accumulator memory which, once the final template element is processed, contains the result of a generalized matrix product defined in the image algebra.