Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of:

• a) providing a semiconductor substrate of a first conductivity type having a reference surface;
• b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface;
• c) forming an insulated gate layer on the sidewall;
• d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench;
• e) forming a conductor that extends from the mesa of the trench to the base of the trench to ohmically contact the second layer of the second conductivity type;
• f) partially filling the trench with a spacer dielectric layer;
• and
• g) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench for ohmic contact with the conductor.

A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of:

• a) providing a semiconductor substrate of a first condustivity type having a reference surface;
• b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface;
• c) forming an insulated gate layer on the sidewall;
• d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench;
• e) partially filling the trench with a spacer dielectric layer;
• f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface;
• g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type;
• h) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench;
• and
• i) forming a field dielectric layer covering the second layer of the second conductivity type in the base of the trench;
• j) opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact;
• and
• k) covering the second current node contact with an interconnect line.