VLSI memory with increased memory access speed, increased memory cell density and decreased parasitic capacitance

An improvement in a memory comprised of a plurality of memory blocks coupled together through metalization lines at each end of each block so that each block is accessed from its ends independently of each other block, each block comprising a plurality of addressable memory cells arranged in logical columns, each column having two corresponding diffusion bit lines disposed along the length of said block of memory cells, said memory cells arranged and configured into four columns with a main diffusion bit line between said second and third columns of memory cells, said improvement comprising:

• a virtual ground decoder for selectively coupling a first and second one of said diffusion bit lines to ground;
• first means disposed at each end of said blocks for selectively coupling each of said first and second ones of said diffusion bit lines to an adjacent one of said four diffusion bit lines;
• second means disposed at each end of said blocks for selectively coupling a precharge on said main diffusion bit line with said adjacent one of said four diffusion bit lines at an end of said block opposite from where said first means selectively couples said first and second one of said selectively grounded diffusion bit lines to said adjacent one of said four diffusion bit lines, said virtual ground decoder being disposed solely at one end of said blocks,
• whereby the length of the circuit path of a signal read from any one of said addressed memory cells through said diffusion bit lines does not exceed in aggregate approximately more nor approximately less than the length of said memory block.

A method for accessing a memory circuit having an array of addressable memory cells organized into blocks of memory cells and including a plurality of diffusion bit lines, virtual ground lines and a main bit line, each of said diffusion bit lines, virtual ground lines and main bit line longitudinally disposed through said blocks of memory cells, each of said blocks having a first and second end, said diffusion bit lines, virtual ground lines and main bit line disposed between said first and second end of each of said blocks, said method comprising the steps of:

• providing a plurality of contact means connected to said virtual ground lines and main bit line at each of said ends of said blocks;
• selectively coupling a ground to one of said plurality of contact means at one end of said block through a metalization line coupling said ends in common;
• selectively coupling a sense amplifier to said main bit line through one of said plurality of contact means at an opposite end of said block through a metalization line coupling said ends in common, said ground and sense amplifier being connected to corresponding ones of said contact means at each of said ends of each of said blocks by corresponding ones of said metalization lines;
• said ground and sense amplifier being selectively coupled to selected ones of said virtual ground lines and main bit line in response to command signals, so that the length of the transmission path in said block to any one of said memory cells within said block from a ground through a corresponding metalization line to said selected virtual ground lines in said block, corresponding bit diffusion line in said block, and main bit line in said block to said sense amplifier never exceeds the approximate length of said selected block of memory cells,
• whereby parasitic capacitance is avoided, memory access speed is increased and the capacity for memory cell density is increased.

A method for accessing a memory comprising a plurality of addressable memory cells arranged in logical columns to form a plurality of blocks of memory cells, each block being coupled by metalization lines with each one of said other blocks and being selectively coupled through said metalization lines to ground and a sense amplifier, each column having two corresponding diffusion bit lines disposed along the length of said block of memory cells, said memory cells arranged and configured into four columns with a main diffusion bit line corresponding to said second and third columns of memory cells, said memory cells being coupled to said diffusion bit lines, said method comprising the steps of:

• selectively coupling a first and second one of said diffusion lines through said metalization lines to ground by a virtual ground decoder at one end of said block;
• selectively coupling said one of said first and second diffusion bit lines to an adjacent diffusion bit line;
• selectively coupling said main diffusion bit line with said adjacent diffusion bit line;
• selectively coupling a sense amplifier through said metalization lines to said main diffusion bit line at an end of said block opposite to said one end of said block which is coupled to said ground,
• wherein one of:
• a) said main diffusion bit line;
• and
• b) said selected one of said first and second diffusion bit lines
• is selectively coupled to said adjacent diffusion bit line through an addressed memory cell,
• whereby the length of the circuit path of a signal read from any one of said addressed memory cells through said diffusion bit lines in said block does not exceed in aggregate substantially more nor substantially less than the length of said memory block.