Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells

Abstract

A one-time, voltage-programmable, read-only memory array in which individual memory cells comprise an insulated-gate, field-effect transistor, the channel of which provides, through a voltage-programmable anti-fuse element, a current path between a reference voltage line and a bitline. In a preferred embodiment, the array comprises a semiconductor substrate having a series of parallel, alternating, minimum-pitch field isolation region and active area strips, a series of parallel, minimum-pitch wordlines overlying and perpendicular to the field isolation region and active area strips, the wordlines being insulated from the active areas by a gate dielectric layer and being dielectrically insulated on their edges and upper surfaces, source/drain junction regions between each wordline pair and field isolation strip pair, a reference voltage line between and coextensive with every other wordline pair that makes anti-fuseable contact to each subjacent pair of cell junctions along its length, antifuseable contact for each cell being made within a trench that extends below junction depth, and is lined with conformal silicon nitride dielectric layer that breaks down when subjected to a programming voltage. A series of minimum pitch bitlines, which run parallel to the wordlines, completes the memory array. Each bitline makes direct contact with each pair of cell junctions along its length. The array is characterized by a non-folded bitline architecture.

Dependencies are inferred from the claim text.