Semiconductor integrated circuit with low-noise output buffers
AssigneeOki Electric Industry Co., Ltd.
InventorSatoru Tanoi
Life of this patent
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Abstract
A semiconductor integrated circuit has output buffers connected in parallel between one or more upper potential lines and one or more lower potential lines. Each output buffer has an output terminal coupled by first and third switching circuits to upper potential lines, and by second and fourth switching circuits to lower potential lines. In the high output state the first switching circuit is switched on, then the third switching circuit is switched on. In the low output state the second switching circuit is switched on, then the fourth switching circuit is switched on. An upper voltage threshold element switches the first switching circuit off above a first threshold output potential. A lower voltage threshold element switches the second circuit off below a second threshold output potential.
Claims18
A semiconductor integrated circuit having first and second upper potential lines for supplying a certain upper potential, first and second lower potential lines for supplying a certain lower potential, and a plurality of output buffers connected in parallel between said upper potential lines and said lower potential lines, each output buffer comprising:
- an output terminal;
- a first switching circuit for switchably coupling said output terminal to the first upper potential line;
- a second switching circuit for switchably coupling said output terminal to the first lower potential line;
- a third switching circuit for switchably coupling said output terminal to the second upper potential line;
- a fourth switching circuit for switchably coupling said output terminal to the second lower potential line;
- and
- a control circuit coupled to switch said first switching circuit on and said second switching circuit and said fourth switching circuit off, then after a certain delay to switch said third switching circuit on, thereby placing said output terminal in a high output state, and to switch said first switching circuit and said third switching circuit off and said second switching circuit on, then after a certain delay switch said fourth circuit on, thereby placing said output terminal in a low output state.
A buffer circuit comprising:
- first and second high potential lines respectively supplying first and second high potential signals;
- first and second low potential lines respectively supplying first and second low potential signals;
- an input terminal for receiving an input signal;
- an output terminal;
- a control circuit connected to said input terminal for generating a control signal in response to the input signal;
- a first output circuit connected between said control circuit and said output terminal for outputting a first output signal to said output terminal in response to the control signal, said first output circuit including,
- a first high potential supplying circuit connected between said first high potential line and said output terminal for outputting the first output signal having a potential lower than that of the first high potential signal, and
- a first low potential supplying circuit connected between said first low potential line and said output terminal for outputting the first output signal having a potential higher than that of the first low potential signal;
- a delay circuit connected to said control circuit and said output terminal for generating a delay signal in response to the control signal and the first output signal;
- and
- a second output circuit connected to said delay circuit for outputting a second output signal to said output terminal in response to the decay signal, said second output circuit including,
- a second high potential supplying circuit connected between said second high potential line and said output terminal for outputting the second high potential signal as the second output signal, and
- a second low potential supplying circuit connected between said second low potential line and said output terminal for outputting the second low potential signal as the second output signal.
Dependencies are inferred from the claim text.