US 5,228,054 A · Power-of-two length pseudo-noise sequence generator with fast offset adjustment

Abstract

A maximal length linear sequence pseudorandom noise (PN) sequence generator for generating an augmented length PN sequence of length 2.sup.N. The PN generator includes circuitry for generating a PN sequence of length 2.sup.N -1 chips. A sequence augmenting circuit is included which inserts at least one additional chip in the PN sequence at a predetermined position within the PN sequence so as to provide an output of an augmented PN sequence of length 2.sup.N chips. The generator may also include sequence shifting circuitry which is responsive to a mask input for providing a predetermined shift in the output augmented PN sequence without incurring a transition period where the shifted output is invalid.

Claims18

Dependent claims

A pseudorandom noise (PN) sequence generator comprising:

means for generating a PN sequence of length 2.sup.N -1 chips;
and
means, operatively connected to said means for generating, for inserting at least one additional chip in said PN sequence, with said means for generating providing an output augmented PN sequence of a length of at least 2.sup.N chips;
wherein N is a positive, non-zero integer;
wherein said means for generating is of a respective state for each chip generated in said PN sequence;
and
wherein said means for inserting comprises:
means for detecting a predetermined state of said means for generating;
and
means for inhibiting a change in state of said means for generating upon detection of said predetermined state.

7 more elements

In a pseudorandom noise (PN) sequence generator capable of generating a PN sequence of a sequence length of 2.sup.N -1 chips, in which N is a positive, non-zero integer, said generator using a linear sequence shift register (LSSR) clocked at a predetermined clock rate by an external clock, said LSSR having a plurality of register stages collectively providing upon each clocking of said LSSR an output corresponding to the state of said LSSR, said LSSR responsive to a disabling input for disabling the generation of said PN sequence, a circuit for augmenting the length of said PN sequence output from said LSSR to a sequence length of 2.sup.N chips comprising:

comparison means for receiving said LSSR state output and a comparison state input representative of a predetermined LSSR state, for comparing said LSSR and comparison states, and providing a corresponding match indication;
and
logic means for receiving said match indication and for providing said disabling input to said LSSR at a predetermined time for one clock cycle upon occurrence of said match indication representative of an equality in said LSSR and comparison states.

In a pseudorandom noise (PN) sequence generator capable of generating a PN sequence of a sequence length of 2.sup.N -1 chips, in which N is a positive, non-zero integer, said generator using a linear sequence shift register (LSSR) clocked at a predetermined clock rate by an external clock, said LSSR having a plurality of register stages each having an output for collectively providing thereat upon each clocking of said LSSR an output bit corresponding to the state of said LSSR, said LSSR having an enable input for enabling/disabling the generation of said PN sequence for each clock cycle, a circuit for augmenting the length of said PN sequence output from said LSSR to a sequence length of 2.sup.N chips comprising;

a first N-bit comparator having a first set of N inputs each coupled to a respective stage output of said LSSR, another set of N inputs each for receiving a predetermined state input bit and an output;
a first clocked delay register having a data input coupled to said comparator output, and an output;
a second clocked delay register having a data input coupled to said first clocked delay register output, and an output;
a first logic circuit having a pair of inputs respectively coupled to said first and second delay register outputs and an output coupled to said LSSR enable input, said first logic circuit generating a signal for enabling and disabling said LSSR for one clock cycle.

1 more element

Dependencies are inferred from the claim text.

Power-of-two length pseudo-noise sequence generator with fast offset adjustment

Life of this patent

Power-of-two length pseudo-noise sequence generator with fast offset adjustment

Life of this patent

Abstract

Claims18