US 5,218,237 A · Circuit forming output pulse a selected delay after initiating pulse

Abstract

A circuit forms a narrow output pulse by charging a first and a second node during the relatively long interval between output pulses. When an initiating pulse is received, both nodes are discharged rapidly. An inverting amplifier which forms the circuit output has its input connected to the second node, and it produces the output pulse as the complement of the voltage level at this node. Time delay elements establish the width of the output pulse. Just before the time for the fall of the output pulse, the first and second nodes are isolated and the second node is then charged to a voltage to turn off the inverting amplifier and drop the output pulse. The initiating pulse is applied to the discharging circuit through a selected one of two paths that have different delays. The circuit is useful in the support circuits for an FET memory of the type that requires a narrow pulse, Row Address Interlock, following an initiating pulse Row Address Set by a short delay in normal memory operations and by a longer delay in memory refresh operation.

Claims15

Dependent claims

A circuit for forming an output pulse (RAI) rising in response to the presence of a binary valued initiating pulse (RAS) and falling a predetermined time thereafter, comprising:

a first node (Node1) and a second node (Node2) and means (T1, T4) for charging the first and second nodes in a predetermined polarity in the absence of the initiating pulse (RAS),
an inverter circuit (INV9) having its input coupled to the second node and having its output connected to produce the output pulse (RAE) in response to the voltage at the second node,
a third node and means (T2) interconnecting the first and second nodes for selectively discharging the second node through the first node and means (T2, T5, T7) responsive to the presence of the initiating pulse for discharging the first and second nodes,
a third node (Node3) and a first delay segment (Inv1-Inv6) connected between the first node and the third node and providing a timing signal at the third node, and a second delay segment (Inv7-Inv8) having its input end coupled to the second node and forming a timing signal at its output end,
the means (T2) interconnecting the first and second nodes being responsive to the timing signal at the third node (Node3) for isolating the second node from the first node before the fall of the output pulse, and
means (T3) connected to respond to the signal at the output end of the second delay segment and connected to the input of the inverter circuit for charging the second node and thereby causing the inverting circuit to drop the output pulse.

3 more elements

A circuit for forming a memory addressing pulse (RAI) in a memory of the type that produces a binary valued signal RSH defining in one state a refresh operation requiring a predetermined delay between the rise of an initiating signal (RAS) and the rise of the memory addressing pulse and defining in the complement state a normal memory operation not requiring the delay, comprising:

first and second terminals for connection to a power supply,
a first node (Node1) and a second node (Node2) and means (T1, T4) for charging the first and second nodes respectively from the first power supply terminal in the absence of the initiating pulse (RAS),
an inverter circuit (INV9) having its input coupled to the second node and having its output coupled to produce the memory addressing pulse (RAI) in response to the voltage at the second node,
means (T2) interconnecting the first and second nodes for selectively discharging the second node through the first node and means (T2, T5, T7) coupled to the first node and responsive to the presence of the initiating pulse for discharging the first and second nodes to the second power supply terminal and thereby raising the memory addressing pulse,
a third node (Node3) and a first delay segment (Inv1-Inv6) connected between the first node and the third node and providing a timing signal at the third node, and a second delay segment (Inv7-Inv8) having its input end connected to the second node and forming a timing signal at its output end,
said means (T2) interconnecting the first and second nodes being responsive to the timing signal at the third node (Node3) for isolating the second node from the first node after the rise of the memory addressing pulse and preparatory for the fall of the memory address pulse, and
means (T3) connected to respond to the signal at the output end of the second delay segment and connected to the input of the inverter circuit for charging the second node and thereby causing the inverting circuit to drop the memory addressing pulse.

4 more elements

Dependencies are inferred from the claim text.

Circuit forming output pulse a selected delay after initiating pulse

Life of this patent

Circuit forming output pulse a selected delay after initiating pulse

Life of this patent

Abstract

Claims15