Semiconductor device having at least two field effect transistors and method of manufacturing the same

A semiconductor device having at least two field effect transistors, comprising:

• a semiconductor substrate with N and P type regions having, respectively, first and second main surface portions;
• an N MOSFET on said second main surface portion of said substrate and formed of a pair of source/drain impurity regions spaced apart from each other in a channel direction on opposite sides of a first gate electrode;
• a P channel MOSFET on said first main surface portion of said substrate and formed of a pair of source/drain impurity regions spaced apart from each other in a channel direction on opposite sides of a second gate electrode;
• wherein sidewalls of insulating material are formed on opposite sides of each of said first and second gate electrodes,
• each impurity region of said N channel MOSFET comprising a region of a first concentration and a region of a second concentration higher than said first concentration, said regions of first and second concentrations intersecting each other beneath said sidewalls, the length of a portion of said region of first concentration beneath said first gate electrode along the second main surface portion in the channel direction being of a value to position a maximum electric field of said first concentration region beneath said first gate electrode;
• and
• wherein each said impurity region of said P channel MOSFET is positioned along the first main surface portion of said substrate to extend beneath a sidewall of, but in non-overlapping relationship with, said second gate electrode.

A method of manufacturing a complementary field effect transistor with an N channel MOSFET including a first gate electrode and a P channel MOSFET including a second gate electrode formed on the same substrate, comprising the steps of:

• forming the first gate electrode and the second gate electrode on the semiconductor substrate having a main surface,
• implanting ions into the main surface of said semiconductor substrate in a direction oblique to said main surface using said first gate electrode as a mask to form an impurity region of relatively low concentration extending beneath said first gate electrode in the main surface of said semiconductor substrate at both sides of said first gate electrode,
• forming sidewall spacers having a width of not less than 0.2 .mu.m in the direction identical to the direction of the channel length at both sidewalls of said first gate electrode and said second gate electrode,
• vertically implanting ions using said sidewall spacers formed at both sidewalls of said first gate electrode as the mask, to form an impurity region having a concentration higher than that of said impurity region of low concentration in the main surface of said semiconductor substrate at both sides of said first gate electrode joining said impurity region of low concentration, and
• vertically implanting ions using said sidewall spacers formed at both sidewalls of said second gate electrode as the mask, to form a P type impurity region in the main surface of said semiconductor substrate at both sides of said second gate electrode in non-overlapping relationship with said second gate electrode.