Self-aligned tungsten-filled via
AssigneeTexas Instruments Incorporated
InventorsJeffrey E. Brighton, Douglas P. Verret
Life of this patent
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Abstract
Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).
Claims7
An apparatus, comprising:
- an elongate conductor formed on a support layer, sides of said conductor extending outwardly from said support layer;
- an outer surface of said conductor having a lateral boundary defined by said sides;
- a first insulator layer formed only on said outer surface, an area of said outer surface not covered by said first insulator layer, said first insulator layer defining first and second edges of said area, third and fourth edges of said area defined by said outer surface lateral boundary;
- a second insulator layer formed to cover all of said sides that adjoin said area;
- a bottom of a via formed by said area, sidewalls of said via formed by said first and second insulator layers;
- and
- conductive material selectively formed in said via to fill said via, an outer surface of said conductive material substantially coplanar with an outer surface of said first insulator layer.
Dependencies are inferred from the claim text.