Fabrication of stabilized polysilicon resistors for SEU control
AssigneeHoneywell Inc.
InventorsMichael S. Liu, Gordon A. Shaw, Jerry Yue
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Abstract
A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.
Claims16
A method for fabricating a polysilicon resistor for use as a cross-coupling resistor in a CMOS static random access memory cell, comprising the following steps:
- providing a semiconductor substrate;
- growing a field oxide layer on said substrate, said field oxide separating a gate region from an interconnected region;
- growing a gate oxide;
- depositing a first polysilicon layer;
- masking and etching a resistor region in said first polysilicon layer at said field oxide layer;
- depositing a second polysilicon layer:
- implanting arsenic ions in said second polysilicon layer at said resistor region to form a resistor having a predetermined resistance value;
- implanting fluorine ions in said second polysilicon layer at said resistance region to stabilize said resistance value;
- and
- performing subsequent semiconductor processes.
In a method for fabricating a polysilicon resistor for use as a cross-coupling resistor in a CMOS static random access memory cell formed on a semiconductor substrate and having a first inverter and a second inverter with said cross-coupling resistor electrically connected between a common gate region of said first inverter and a common drain connection of said second inverter, the improvement of making said polysilicon resistor more reproducible, comprising the following steps:
- growing a field oxide layer on said substrate, said field oxide defining a gate region;, and an interconnected region;
- growing a gate oxide;
- depositing a first polysilicon layer;
- masking and etching a resistor region in said first polysilicon layer at said field oxide layer;
- depositing a second polysilicon layer:
- implanting impurities in said second polysilicon layer at said resistor region to achieve a predetermined resistivity value;
- implanting fluorine ions in said second polysilicon layer to stabilize said resistivity value;
- and
- performing subsequent semiconductor processing steps.
A method for fabricating a polysilicon resistor for use as a cross-coupling resistor in a CMOS static random access memory cell, comprising the following steps:
- providing a semiconductor substrate;
- growing a field oxide layer on said substrate, said field oxide separating a gate region form an interconnected region;
- growing a gate oxide;
- depositing a first polysilicon layer;
- masking and etching a resistor region in said first polysilicon layer at said field oxide layer;
- depositing a second polysilicon layer:
- implanting impurity ions in said second polysilicon layer at said resistor region to form a resistor having a predetermined resistance value;
- implanting fluorine ions in said second polysilicon layer at said resistance region to stabilize said resistance value;
- and
- performing subsequent semiconductor processes.
Dependencies are inferred from the claim text.