Wiring method for semiconductor integrated circuits

A wiring method for semiconductor integrated circuits having a multilayered wiring structure, comprising the steps of:

• allotting the wires requiring consideration of delay time and the wires not requiring consideration of delay time for semiconductor integrated circuits automatically to the multilayered wiring structure;
• counting the number of points where the wires requiring consideration of delay time cross wires;
• setting a reference value of the number of points where the wires requiring consideration of delay time cross wires within a limited value of delay time;
• comparing the reference value with the number of points where each of the wires requiring consideration of delay time crosses wires;
• and
• increasing the crossing points by circumventing the wiring route and/or adding an antenna open at an end thereof thereby to substantially equalize the number of points to the reference value with regard to the wires requiring consideration of delay time having a smaller number of points of crossing than the reference value.