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US 5,212,103 AGranted
Method of making a heterojunction bipolar transistor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTeruyuki Shimura
Life of this patent
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Abstract
A semiconductor device includes an n.sup.+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n.sup.+ layer without alloying and an externally accessible base region produced in the neighborhood of the emitter electrode by diffusion using the emitter electrode and an insulating side wall film as a diffusion mask.
Claims15
A method of producing a semiconductor device comprising:
- epitaxially growing a plurality of layers of GaAs and AlGaAs and n.sup.+ type InGaAs layer as the final layer;
- producing a refractory metal emitter electrode on and making ohmic contact with said InGaAs layer without alloying;
- selectively etching said n.sup.+ type InGaAs layer using said emitter electrode as a mask;
- depositing a first insulating film on said emitter electrode and n.sup.+ type layer and forming side walls on the side surfaces of said emitter electrode and said n.sup.+ type InGaAs layer by anisotropic etching of the insulating film;
- depositing a doped oxide on the surface exposed by the selective etching of said n.sup.+ type InGaAs layer;
- selectively diffusing dopants from said doped oxide into said layers using said emitter electrode and said side walls as a diffusion mask to form an external access to a base region in said layer;
- converting portions of said base region into electrically insulating regions by ion implantation using a photoresist mask;
- depositing a second insulating film on said emitter electrode and selectively etching the second insulating film to expose a surface of said emitter electrode;
- forming at least one opening in the second insulating film isolated from said emitter electrode, exposing said base region;
- and
- depositing a metal base contact in the opening contacting said base region.
8 more elements
A method of making a heterojunction bipolar transistor comprising:
- successively epitaxially growing on a semiconductor substrate an n type collector, at least one graded p type AlGaAs layer for forming a base, an n type AlGaAs emitter layer, and n.sup.+ type InGaAs cap layer;
- depositing and patterning a refractory metal emitter electrode on the cap layer;
- depositing a first electrically insulating film on the cap layer and emitter electrode;
- selectively etching the first electrically insulating layer and the epitaxial graded layer to leave the first electrically insulating film on side walls of the emitter electrode and to expose the graded n type AlGaAs layer for forming a base and to expose a top surface on the emitter electrode;
- depositing a p type dopant source film on the exposed emitter electrode and graded layer;
- diffusing impurities from the dopant source film into the graded layer to form a p type base region self-aligned with the emitter electrode;
- removing the dopant source film and depositing a second electrically insulating film to flatten the exposed surface of the device;
- selectively etching the second insulating film to expose the top surface of the emitter electrode;
- forming at least one opening in the second insulating film isolated from the emitter electrode exposing the base region;
- and
- depositing a metal base contact in the opening on the base region.
8 more elements
Dependencies are inferred from the claim text.