Semiconductor device with input protection circuit of high withstand voltage
AssigneeKabushiki Kaisha Toshiba
InventorsKazuhiko Kakizoe, Hiroaki Murakami
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Abstract
A semiconductor device equipped with an input protection circuit having a high withstand voltage and an improved reliability. The input protection circuit of the semiconductor device includes a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device, where one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Claims22
An input protection circuit for a semiconductor device using a FET, comprising:
- a semiconductor substrate;
- a source region formed in the semiconductor substrate;
- a drain region formed in the semiconductor substrate;
- a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device;
- wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
A semiconductor device, comprising:
- a FET;
- and
- an input protection device, including:
- a semiconductor substrate;
- a source region formed in the semiconductor substrate;
- a drain region formed in the semiconductor substrate;
- a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device;
- a gate electrode provided on the gate insulation film;
- and
- an additional gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the additional gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device;
- wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Dependencies are inferred from the claim text.