Insulated gate GTO thyristor
AssigneeKabushiki Kaisha Toshiba
InventorsTakashi Shinohe, Masaki Atsuta, Akio Nakagawa
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Abstract
According to this invention, there is disclosed an insulated gate GTO thyristor comprising a pnpn structure including a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. The thyristor has a first gate electrode contacting the p-type base layer and a second gate electrode formed on a channel region of the p-type base layer through a gate insulating film. An n+-type layer of the n-type emitter layer immediately below a cathode electrode and an n--type layer of the n-type emitter layer contacting the channel region are formed in different manufacturing steps, and an emitter breakdown voltage and the threshold voltage of the second gate electrode are optimally set.
Claims14
An insulated gate GTO thyristor comprising:
- a first emitter layer of a first conductivity type;
- a first base layer of a second conductivity type contacting said first emitter layer;
- a second base layer of the first conductivity type in said first base layer, said second base layer having a surface portion which is not in contact with said first base layer;
- a second emitter layer of the second conductivity type which is not in contact with the first base layer and defining a channel region of the second base layer as a region of the second base layer which is between said first base layer and said second emitter layer;
- a first main electrode coupled with said first emitter layer;
- a second main electrode coupled with said second emitter layer;
- a first gate electrode arranged on said surface portion of said second base layer;
- a second gate electrode insulatively disposed above said channel region;
- and
- said second emitter layer comprising a first impurity doped layer immediately below said second main electrode, and a second impurity doped layer smaller in dopant concentration than said first impurity doped layer, said second impurity doped layer being arranged to partially overlap said first impurity doped layer and said channel region.
An insulated gate GTO thyristor comprising:
- a first emitter layer of a first conductivity type;
- a first base layer of a second conductivity type contacting said first emitter layer;
- a second base layer of the first conductivity type in said first base layer, said second base layer having a surface portion which is not in contact with said first base layer;
- a second emitter layer of the second conductivity type which is not in contact with the first base layer and defining a channel region in the second base layer as a region of the second base layer which is between said first base layer and said second emitter layer;
- a first main electrode being in contact with said first emitter layer;
- a second main electrode being in contact with said second emitter layer;
- a first gate electrode being in contact with said second base layer;
- a dielectric film on said channel region;
- a second gate electrode on said film;
- and
- said second emitter layer comprising a first impurity doped layer immediately below said second main electrode, and a second impurity doped layer which partially overlaps said channel and said first impurity doped layer at a portion of said first impurity doped layer contacting at least said channel region, and which is smaller in depth than said first impurity doped layer.
Dependencies are inferred from the claim text.