Static RAM cell with conductive straps formed integrally with thin film transistor gates
AssigneeSharp Kabushiki Kaisha
InventorAlberto O. Adan
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Abstract
A static RAM cell including first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor.
Claims4
A static RAM cell comprising a flip-flop circuit having two inverters connected to each other, and two access transistors for connecting nodes of said flip-flop circuit to bit lines;
- wherein said inverters are formed on a semiconductor substrate and comprise first and second bulk transistors respectively having gate electrodes extending to a device isolating region, and thin film transistors having gate electrodes, said thin film transistors being formed on said first and second bulk transistors;
- wherein said access transistors comprise third and fourth bulk transistors having source/drain regions formed adjacent said device isolating region;
- and
- wherein said gate electrodes of said first and second bulk transistors are connected to said source/drain regions of said third and fourth bulk transistor, respectively through first and second conductive strap layers, said first and second conductive strap layers being formed integrally with the gate electrodes of said thin film transistors.
Dependencies are inferred from the claim text.