Method of fabricating EPROM device with metallic source connections

Process for the fabrication of an integrated EPROM device comprising an array of unitary memory cells, each having a gate structure between a source area or source region and a drain area or drain region of a semiconductor substrate, arranged in pairs in rows and columns, the control gates of the cells of the same row being electrically connected together by a respective continuous gate line, the drain area of the cells being individually contacted through drain contacts and the drain contacts of cells belonging to the same column being electrically connected together by a respective drain line, the source regions of adjacent cells of the same column and belonging to pairs of cells of two distinct adjacent rows of the array being electrically connected in common, a field isolation structure separating the drain areas and gate structures of one cell from those of an adjacent cell positioned on the same row, characterized in that it comprises the following steps:

• forming field isolation structures between cells of the same row of the array in the form of continuous isolation strips, spaced apart and parallel, which extend uninterrupted along the whole column length of said array of cells;
• forming gate structures in the form of gate lines, spaced apart and parallel, running perpendicularly in relation to the isolation strips below and having dielectric spacers formed along side walls,
• conformally depositing a matrix metal layer;
• depositing a layer of planarization material;
• blanket maskless etching the layer of planarization material until the peaks of the metal layer below previously deposited in a comformal manner are exposed while leaving residual strips of said planarization material within hollows of said metal layer;
• forming a photoresist drain separation mask having openings in the areas where the strips of residual planarization material running over the drain areas of cells belonging to each row of said array cross over the isolation strips;
• removing by etching the residual planarization material of said strips through said openings of the mask and removing the latter;
• etching, under essentially isotropic conditions, said metal layer using said residues of planarization material as a mask, leaving pillar shaped contact metal residues of said metal layer, self-aligned in relation to adjacent gate structures, over drain areas of all the unitary cells and a seam-like metal residue, having a pillar shaped cross-section, in the form of a continuous line, self-aligned in relation to adjacent gate structures, running over the source areas of all the cells belonging to the each row of said array;
• removing said residues of planarization material used as a mask during the previous etching step;
• depositing an insulation layer of dielectric material;
• forming a photoresist mask and etching the said isolation layer of dielectric material through said mask, to expose the peaks of said pillar shaped contact metal residues formed over the drain area of the cells and removing said mask;
• depositing a second metallic layer to interconnect said pillar shaped, drain contact metal residues;
• forming a mask to define interconnection drain lines respectively for the cells belonging to each column of said array and removing said mask.