US 5,210,041 A · Process for manufacturing semiconductor integrated circuit device

Abstract

A wafer manufacturing process for a semiconductor integrated circuit device, including testing the semiconductor wafer at a unit of chip each time a predetermined treating step is performed. The test results are feed to a computer control for restricting succeeding treatments or further testing of chip or chips based on the test results and the predetermined number of chips to be produced. Semiconductor wafer(s) is/are loaded for manufacture on the basis of the number of chips to be produced, taking into account of any losses created by defective chips detected during each testing step and any excess created by additional semiconductor wafers loaded in response to shortages created by defects. The excess chips are monitored by the computer control and any succeeding treatments or further testing of the excess chips are halted to save time and manufacturing costs.

Claims12

Dependent claims

In a wafer process for manufacturing a semiconductor integrated circuit device by subjecting a semiconductor wafer to a plurality of treating steps,

a process for manufacturing a semiconductor integrated circuit device, comprising the repeated steps of:
testing said semiconductor wafer at a unit of chip each time a predetermined one of said treating steps is ended;
preparing control data for loading another semiconductor wafer on the basis of the data of each of said chips and feeding the control data back to a predetermined treating step of the wafer process if it is decided in accordance with the data of each chip based upon the test results that the number of non-defective chips at the testing stage is short of the necessary number for the testing step;
performing said tests of the semiconductor wafers including said another one;
and
monitoring the data of the chips of the initially loaded semiconductor wafer and the added semiconductor wafer synthetically and feeding control data for loading another semiconductor wafer, each time it is decided that the number of non-defective chips is short of the necessary number for the testing step in its entirety, back to a predetermined treating step of the wafer process.

3 more elements

In a wafer process for manufacturing a semiconductor integrated circuit device by subjecting a semiconductor wafer to a plurality of treating steps,

a process for manufacturing a semiconductor integrated circuit device, comprising the commands of:
testing said semiconductor wafer at a unit of chip each time a predetermined one of said treating steps is ended;
preparing control data for loading another semiconductor wafer on the basis of the data of each of said chips and feeding the control data back to a predetermined treating step of the wafer process if it is decided in accordance with the data of each chip at the testing stage that the number of non-defective chips is short of the necessary number for the testing step;
repeating performing said tests of the semiconductor wafers including said another one, monitoring the data of the chips of the initially loaded semiconductor wafer and the added semiconductor wafer synthetically, and feeding control data for loading another semiconductor wafer, each time it is decided that the number of non-defective chips is short of the necessary number for the testing step in its entirety, back to a predetermined treating step of the wafer process;
preparing control data for restricting the chip to be subjected to a treating step before the test and a testing step, if it is decided as a result of the data of said chips that the number of non-defective chips exceeds the necessary number at the testing stage, and feeding said control data as the treating data for another succeeding semiconductor wafer back to the treating step and testing step preceding the test by at least one;
and
preparing control data for restricting a chip to be subjected to the treating step after the test on the basis of the data of said chip, and feeding said control data back to a treating step preceding the test by at least one.

4 more elements

Dependencies are inferred from the claim text.

Process for manufacturing semiconductor integrated circuit device

Life of this patent

Process for manufacturing semiconductor integrated circuit device

Life of this patent

Abstract

Claims12