Method for optimizing automatic place and route layout for full scan circuits

In a computer-aided circuit design system for placing circuit cells comprising flip-flop circuits, buffers, and combinatorial circuit elements within an integrated circuit and routing connections between said circuit cells, a method of placing said circuit cells in said integrated circuit comprising the steps of:

• receiving a schematic diagram of a block of said circuit cells to be placed and routed;
• representing the flip-flop circuits, buffers and combinatorial circuit elements as a multiplicity of standard cells;
• routing at least one conductor across the circuit cells representing the flip-flop circuits, said conductor transmitting at least one global signal across the circuit cell;
• terminating said conductor at input and output terminals on opposite sides of the circuit cells;
• receiving at least one loading value table comprising standard load values representing the conductors of said flip-flop circuits;
• placing the circuit cells so that all flip-flop circuits lie in rows with other flip-flop circuits, said rows having left and right ends;
• computing buffer amplification values for said buffers from the standard load values in the loading tables by adding the standard values representing the flip-flop circuits placed in said rows to form a total flip-flop load;
• placing said buffers at said left and right ends of said rows with said flip-flop circuits on the integrated circuit, said buffers driving the conductors according to the total flip-flop load computed to be driven;
• and,
• updating said schematic by back-annotating said conductors and total flip-flop load into said schematic.