Output pad electrostatic discharge protection circuit for MOS devices

In a CMOS input buffer device that includes an input lead coupled to an input pad, an input protection circuit comprising:

• an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a gate, a first output lead coupled to the input pad, and a second output lead;
• said gate and second output lead of said output PMOS transistor being coupled together to a first voltage source node;
• said gate and second output lead of said output NMOS transistor being coupled together to a second voltage source node;
• and
• a second PMOS transistor, including a gate coupled to said first voltage source node, a first output lead coupled to the input pad, and a second output lead coupled to said gate of said output NMOS device;
• whereby a positive ESD potential at said input pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor;
• the input buffer device being protected thereby from damage from said positive ESD potential at said input pad that would occur int he absence of said input protection circuit.

In a CMOS output buffer device having first and second input/output drivers, each driver having an input lead and an output lead, an output protection circuit comprising:

• an output pad;
• an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a first output lead coupled to said output pad, said PMOS transistor further including a second output lead, and a gate, said gate coupled to the output lead of the first input/output driver;
• said NMOS transistor further including a second output lead and a gate, said gate coupled to the output lead of the second input/output driver;
• and
• a second PMOS transistor, including a gate coupled to a voltage source node in the circuit, a first output lead coupled to said output pad, and a second output lead coupled to said gate of said output NMOS device;
• whereby a positive ESD potential at said output pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor;
• the output buffer device being protected thereby from damage from said positive ESD potential at said output pad that would occur in the absence of said output pad protection circuit.