DRAM Cell with trench capacitor and vertical channel in substrate
AssigneeTexas Instruments Incorporated
InventorsPallab K. Chatterjee, Satwinder Malhi, William F. Richardson
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Abstract
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.
Claims28
A device comprising:
- (a) a substrate with a trench formed therein;
- (b) material for storing a signal within said trench substantially insulated from said substrate;
- and
- (c) a field effect transistor having a channel in said substrate and positioned to provide channel current flow substantially along the walls of said trench, said field effect transistor being conductively connected to said material for storing a signal.
A device comprising:
- (a) a substrate with a trench formed therein;
- (b) a capacitor having a plate within said trench substantially insulated from said substrate;
- and
- (c) a field effect transistor positioned to provide current flow substantially along the side walls of said trench, said field effect transistor having a channel region formed in said substrate, said field effect transistor being conductively connected to said plate of said capacitor.
A device comprising:
- (a) a substrate having a trench formed therein;
- (b) an insulating layer on the walls of said trench;
- (c) a capacitor having a first plate formed on said insulating layer, said substrate serving as a second plate;
- (d) a transistor having a gate in said trench at least partially below the surface of said substrate, the portion of said gate below said surface being adjacent to but insulated from a portion of the walls of said trench, said gate controlling current in a channel region in said substrate along the walls of said trench, and said transistor being conductively connected to said first plate.
A memory cell comprising:
- (a) a substrate having at least a first second and third surfaces, said third surface extending between first and second surfaces and said third surface extending into said substrate at an angle from said first surface;
- (b) an insulating layer on at least a portion of said third surface;
- (c) a conductive material formed on said insulating layer serving as a first capacitor plate, said substrate serving as a second capacitor plate;
- (d) a transistor having a channel in said substrate along said third surface, having a source connected to said first plate, having a drain connected to a bit line and having a gate connected to a word line.
A memory cell comprising:
- (a) a substrate having at least a first second and third surfaces, said third surface extending between first and second surfaces and said third surface extending into said substrate at an angle from said first surface;
- (b) an insulating layer on at least a portion of said third surface;
- (c) a conductive material formed on said insulating layer serving as a first capacitor plate, said substrate serving as a second capacitor plate;
- (d) a transistor having a channel along said third surface, having a source connected to said first plate, having a drain connected to a bit line and having a gate connected to a word line.
The memory cell of 17 wherein said second and third surfaces are surfaces of a trench formed in said substrate and said first surfaces is a major face of said substrate.
The memory cell of 18 wherein said trench has a major axis perpendicular to said first surface of said substrate.
A cross point memory cell array on a substrate, comprising:
- (a) a plurality of parallel first conductor lines on said substrate;
- (b) a plurality of parallel second conductor lines crossing said first conductor lines but insulated therefrom;
- and
- (c) a plurality of cells, one cell at each of said crossings, each of said cells including a trench in said substrate extending from said crossing, a storage node within said trench substantially insulated from said substrate and a field effect transistor having a channel in said substrate and positioned to provide channel current flow substantially along the walls of said trench, said field effect transistor being conductively connected to said storage node.
A cross point memory cell array on a substrate, comprising:
- (a) a plurality of parallel first conductor lines on said substrate;
- (b) a plurality of parallel second conductor lines crossing said first conductor lines but insulated therefrom;
- and
- (c) a plurality of cells, one cell at each of said crossings, each of said cells including a trench in said substrate extending from said crossing, a storage node within said trench substantially insulated from said substrate and a field effect transistor having a channel and positioned to provide channel current flow substantially along the walls of said trench, said field effect transistor being conductively connected to said storage node.
The array of claim 28 wherein said channel current flow is into one of said first conductor lines and the gate of said transistor is connected to one of said second of said conductor lines.
Dependencies are inferred from the claim text.