Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions

#1. Field of the Invention

#The present invention relates to an electrostatic discharge protection circuit which uses a MOS device with non-lightly doped source and drain regions for protecting other MOS devices with lightly doped source and drain regions on an integrated circuit.

#2. Description of the Prior Art

#FIG. 1 is a cross section of an N channel lightly doped drain (LDD) MOS device according to the prior art.

#FIG. 2 is an ESD protection circuit using an MOS device with LDD regions according to the prior art.

#FIGS. 3A through 3C are a cross-section view of a N channel LDD device, a complementary P channel device, and a non-LDD device respectively after the gates of each device have been formed according to the present invention.

#FIGS. 3 through 7 show a sequential series of structures in a CMOS fabrication process. The purpose of the sequence is to illustrate how an N channel non-LDD devices can be simultaneously fabricated with other LDD MOS devices on an integrated circuit in a CMOS process flow.

#Referring to FIGS. 3A through 3C, cross section views of an N channel LDD device, a complementary P channel device, and a non-LDD device are shown respectively at an initial stage in the fabrication process. In FIG. 3A, the N channel LDD device 100 includes a gate oxide 101 and a gate 102 built on a P type substrate 104. In FIG. 3B, the P channel device 110 includes a gate oxide 113 and a gate 114 which is built on an N well 112 within substrate 104. In FIG. 3C, the non-LDD device 120 includes a gate oxide 121 and a gate 122 built on substrate 104.

#Referring to FIGS. 4A through 4C, cross sectional views of the N channel LDD device, the complementary P channel device, and the non-LDD device are respectively shown after a light N type doping implant. In FIG. 4A, a first N-lightly doped region 105 and a second N- lightly doped region 106 are formed adjacent gate 102 during the N dopant implant. In FIG. 4B, prior to the N dopant implant, a resist layer 116 is placed over the device. As a result, the N type well 112 is protected from the N type implant and its dopant concentration level remains unchanged. In FIG. 4C, a resist 124 is placed around the gate 122 a predetermined lateral distance from the gate. The lateral distance should be equal to or greater than the later to be formed spacer oxide plus an allowance for processing alignment and lateral dimension variance. In a preferred embodiment, the lateral distance of the resist from the gate is approximately 2.0 microns. Accordingly, after the N implant, lightly doped N regions 125 and 126 are formed the predetermined lateral distance from the gate 122. Thereafter, the resist 124 and 116 are removed.