Semiconductor memory device with a stacked capacitor

#The present invention generally relates to a dynamic random access memory (DRAM) in a semiconductor memory device, and more particularly, to a structure of a diffusion layer in contact with a storage node of DRAM provided with a stacked capacitor.

#Most of DRAM devices are provided with a plurality of memory cells each having one transistor and one capacitor. An amount of 10 the electric charges accumulated in the capacitor of the memory cell determines either one state of logic "low", i.e., "0" or logic "high", i.e., "1", which state is stored into the capacitor and then read out through the transistor. Here, the more the amount of the accumulated charges is, the better the sensing operation of information in the memory device is. Thus, to enhance the device performance, the capacitance of the capacitor should be made as large as possible. This is accomplished by increasing the plate area of the capacitor or decreasing the plate spacing thereof, under a given available dielectric constant of the dielectric. The decrease of the plate spacing of the capacitor, however, has itself the limit. Also the plate area thereof is minimized in proportional to the decrease of device area occupied by the high-density memory device. As a result, if the plane capacitor is employed in the high-density memory devices, the capacitance suitable for high-density memory device is not achieved. In attempt to solve this problem, the trench capacitor, in three-dimension, formed in a substrate, and the stacked capacitor, in three-dimension, formed on the substrate are contrived.

#Referring to FIG. 1 illustrating the layout of the semiconductor memory device with a stacked capacitor, an active region 2 and a word line 4 are respectively extended in horizontal direction and vertical direction. A first and a second contact regions 6, 8 are disposed over the active region 2. A bit line 10 is extended in horizontal direction, with being contacted with the second contact region 8. Also a storage electrode region 12 is disposed over the active region 2, with being contacted with the first conducting region 6. A plate electrode region 14, wholly covering the storage electrode region 12, is disposed over the storage electrode region 12.

#The above objects and other advantages of the present invention will become more apparent by describing in detail the preferred embodiments of the present invention with reference to the attached drawings in which:

#FIG. 1 illustrates the general layout of the semiconductor memory device provided with the staked capacitor;

#FIG. 2 illustrates the cross sectional view of the FIG. 1;

#FIG. 4 illustrates the cross sectional view of the embodiment according to the present invention, when mis-alignment is generated during the manufacture of the DRAM having the layout of the FIG. 1. As shown in FIG. 4, a first and a second field oxide layers 31, 32, a first source and drain regions 34, 36, a gate insulating layer 38, a gate 40 and an insulating interlayer 46 are sequentially formed over the substrate 30 of the first conductivity type. After forming the patterns for apertures corresponding to first and second contact regions 42, 44, selective etching of the insulating interlayer 46 is carried out, until the partial top surface of the substrate is exposed. Thereby the apertures are formed. The part of the first contact region 42, however, may be positioned outside of the border of the first source region 34, by the mis-align generated during the aligning of mask pattern for the contact regions. Hence the impurity ions of the second conductive type is implanted into the first contact region 42, to form the second source region 48. Herein the impurity ions concentration and the diffusion depth of the second source 48 are similar to the concentration of and diffusion depth of the first source region 34. This results in, albeit the mis-align is generated, that the entire bottommost surface of the first contact region 42 is surrounded by the first and second source regions. As an example, the concentration of the substrate and the concentrations of the first and second source regions are respectively in the range of 10.sup.14 -10.sup.16 ions/cm.sup.3, and 10.sup.18 -10.sup.21 ions/cm.sup.3. Thereafter by known process, the stacked capacitor, comprising a first polysilicon layer 50, a dielectric layer 52 and a second polysilicon layer 54, and bit lines of metal layers are manufactured and the completed semiconductor memory device is achieved.

#Referring to the FIG. 5 illustrating another embodiment according to the present invention, the second source region 48 partially overlapping the first source region 34 is formed by the ion-implantation, as shown in FIG. 4. Thereafter, the impurity ions of the first conductivity type are implanted toward the first contact region 42, in order to form a diffusion region 58 of the first conductivity type surrounding the second source region 48. The concentration of impurity ions of the diffusion region 58 corresponds to that between the concentration of the substrate and the concentration of the first or second source region. As an example, the concentration of the diffusion region 58 is employed in the range of 10.sup.16 -10.sup.19 ions/cm.sup.3. The diffusion region 58 blocks, for electrons generated by the incident .alpha. particles into the substrate, to enter the storage node layer through the source regions in the substrate. Thereby the influence of the .alpha. particles on the storage electrode is suppressed.

#FIG. 6 illustrates the cross sectional view of still another embodiment according to the present invention, wherein the DRAM cell does not have mis-align generated during the manufacture thereof, or density thereof is not high. In the above case, the second source region of FIGS. 4, 5 is not needed any more, because the contact region of the storage electrode is formed within the source region 34a. Accordingly the ion-implantation of the impurity having the conductivity type opposite to that of the source region 34a follows the ion-implantation for the source region 34a. Thereby a diffusion region 58a of the first conductivity type is formed. The concentration of the impurity of the diffusion region 58a must be lower and higher respectively than that of the source region and that of the substrate. In the present embodiment of FIG. 6, the concentration of the substrate is 10.sup.14 -10.sup.16 ions/cm.sup.3, the source region is 10.sup.18 -10.sup.21 ions/cm.sup.3, and the diffusion region 58a 10.sup.16 -10.sup.19 ions/cm.sup.3.