Wafer scale integrated circuit and method of forming signal propagation path therein

Abstract

A wafer scale integrated circuit includes a plurality of functional circuit blocks arranged in rows on a wafer, each functional circuit block having four corners, and a signal propagation path (spiral) serially connecting some of the plurality of functional circuit blocks. Each functional circuit block is arranged in a zigzag manner such that at least two corners of a functional circuit block in one row are located approximately in the center of respective sides of corresponding functional circuit block in a row adjacent to that row. As a result, it is possible to reduce the number of branch signal paths to the lowest possible value when forming the spiral, and thus facilitate an external control for forming the spiral to thereby shorten a processing time needed for the control, while increasing a utilization efficiency of non-defective chips.

Dependencies are inferred from the claim text.