US 5,206,532 AGranted

Buried contact between polysilicon gate and diffusion area

AssigneeMicron Technology, Inc.

InventorMartin C. Roberts

Life of this patent

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Abstract

A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure. The migration region extends laterally away from the gate layer to make contact with a remote diffusion region, thereby effecting with the polysilicon interconnect structure the desired buried contact.

Claims12

Dependent claims

A buried contact between a polysilicon gate and a diffusion region of a first conductivity type, said polysilicon gate having both a bottom surface and a plurality of vertical sides above the bottom surface and being disposed on a first insulative layer on a substrate, said diffusion region being located in the surface of the substrate remote from the polysilicon gate, said buried contact comprising:

(a) a polysilicon interconnect structure, having both a bottom surface and a plurality of vertical sides above the bottom surface, disposed both above the first insulative layer on the substrate and against at least one of said plurality of vertical sides of the gate and contacting both the surface of the substrate and the first insulative layer, said polysilicon interconnect structure contacting the surface of the substrate to define thereat a surface current pathway interface located at the surface of said substrate remote and separated from the diffusion region;
(b) a migration region of the first conductivity type disposed in the surface of the substrate below and in contact with all of said surface current pathway interface, said migration region extending laterally from said surface current pathway interface away from the gate to contact the diffusion region;
and
(c) a second insulative layer disposed against at least one of said plurality of sides of said polysilicon interconnect structure remote from the gate, said second insulative layer contacting the surface of the substrate adjacent said surface current pathway interface to define thereat an insulator contact surface, said insulator contact surface including at least a portion of the boundary between said diffusion region and said migration region;
wherein said surface current pathway interface and said insulator contact surface are substantially coplanar.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/748,796Filed 22 Aug 1991 · division
Priority: 3 Oct 1990
Granted: 27 Apr 1993
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 20/021
Manufacture or treatment: of interconnections within wafers or substrates
Y10S 257/904
FET configuration adapted for use as static memory cell: with passive components,, e.g. polysilicon resistors
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by
Y10S
Technical subjects covered by former uspc cross-reference art collections [xracs] and digests