Semiconductor integrated circuit device
AssigneeNEC Corporation
InventorHirotoshi Mine
Life of this patent
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Abstract
A semiconductor integrated circuit device wherein a plurality of macros are formed on a master chip and wirings are provided striding across a specific macro and thereon through a thick insulating film, whereby parasitic capacitance is reduced and high speed operation of a circuit is attained.
Claims6
A semiconductor integrated circuit wherein a plurality of macros are formed on a master chip in which a plurality of basic cells are regularly arranged, each of said macros being a functional block registered in a library, said integrated circuits having at least one interlayer insulating film, an insulating film substantially thicker than said interlayer insulating film selectively formed on a specific macro, a power line formed on the thick insulating film and extending across the specific macro, said power line being connected to said specific macro through a contact hole formed in said thick insulating film, and signal lines interconnecting the macros other than said specific macro, said signal lines extending across said thick insulating film disposed on said specific macro.
Dependencies are inferred from the claim text.