Method of making single layer personalization

In a gate array having parallel rows of base cells, A process for fabricating a connection between base cells of different rows in a gate array comprising the steps of:

• providing a gate array having rows of base cells, wherein each base cell comprises a plurality of transistors, wherein a space is between said rows, wherein columns of vertical segments of a first conductive layer are fabricated between the rows, such that said segments are substantially perpendicular to said rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments,
• designing a routing path between one of said base cells of different rows, wherein said routing path comprises portions which are vertical and horizontal to said rows;
• and
• coupling said base cells of different rows, wherein said vertical portions of said routing path comprise said vertical segments coupled together with a second conductive material using their respective vias, such that said base cells of different rows are coupled at said second conductive layer by using a portion of said first conductive layer.

A process for fabricating an electrical connection between base cells of different rows comprising the steps of:

• providing a gate array having rows of base cells, wherein said base cells comprise a plurality of transistors, wherein said plurality can be coupled in multiple schemes to perform a simple logic function, wherein a space exists between said rows, wherein segments of a first conductive layer are fabricated between the rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments:
• designing a logic function consisting of connection path of said segments of said first conductive layer for coupling said base cells of different rows and a connection scheme for coupling said plurality;
• and
• coupling said path segments and said plurality using said vias and a second conductive layer, such that said base cells of different rows are coupled at said second conductive layer utilizing a portion of said first conductive layer.

A process for fabricating a base cell for a designated function in a gate array comprising the steps of:

• providing a gate array having rows of base cells, wherein each base cell is fabricated to include a plurality of transistors and a plurality of segments of a first conductive material coupled to said plurality of transistors, said cell having an insulative layer disposed on said segments, said insulative layer having vias over each end of said segments, such taht each cell is fabricated up to the via level;
• defining a routing path between the transistors of said base cell, wherein said routing path comprises at least one of said segments and at least two of said transistors, such that said cell is capable of performing the designated function when said segments and said are coupled;
• and
• coupling said transistors of the base cells, wherein said portions of said routing path are coupled together with a second conductive material by their respective vias, such that said base cell is fabricated to perform its designated function at said second conductive layer using a portion of said first conductive layer.