Lateral type semiconductor device having a structure for eliminating turning-on of parasitic MOS transistors formed therein

A bipolar transistor having a base, an emitter and a collector, the base connected to one of an emitter and a collector to form a diode, comprising:

• a semiconductor layer of a first conductivity type, said semiconductor layer having upper and lower major surfaces and defined with a device region of the first conductivity type, the device region serving as a base region of the bipolar transistor and having an upper major surface coincident to the upper major surface of the semiconductor layer;
• an isolation region of a second, opposite conductivity type, said isolation region having an upper major surface coincident to the upper major surface of the semiconductor layer and formed in the semiconductor layer such that the isolation region surrounds the device region;
• an emitter region of the second conductivity type formed in a part of the device region, said emitter region having an upper major surface coincident to the upper major surface of the semiconductor layer;
• a collector region of the second conductivity type and formed in part of the device region with a separation from the emitter region between the emitter region and isolation region, said collector region having an upper major surface coincident to the upper major surface of the semiconductor layer;
• a first insulator layer having upper and lower major surfaces and provides on the upper major surface of the semiconductor layer;
• a first contact hole formed in the first insulator layer in correspondence to the emitter region for exposing the upper major surface of the emitter region;
• a second contact hole formed in the first insulator layer in correspondence to the collector region for exposing the upper major surface of the collector region;
• a third contact hole formed in the first insulator layer in correspondence to the base region for exposing the upper major surface of the base region;
• a first conductor pattern having upper and lower major surfaces and provided on the upper major surface of the insulator layer in correspondence to the emitter region with an electrical contact to the emitter region;
• a second conductor pattern having upper and lower major surfaces and provided on the upper major surface of the insulator layer in correspondence to the collector region with an electrical contact to the collector region;
• a third conductor pattern having upper and lower major surfaces and provided on the upper major surface of the insulator layer in correspondence to the base region with an electrical contact to the base region;
• a second insulator layer having upper and lower major surfaces and provided on the upper major surface of the first insulator layer to bury the first through third conductor patterns;
• a fourth contact hole formed in the second insulator layer in correspondence to the first conductor pattern for exposing the upper major surface of the first conductor pattern;
• a fourth conductor pattern having upper and lower major surfaces and provided on the upper major surface of the second insulator layer, said fourth conductor pattern being provided with an electrical contact on the exposed upper major surface of the first conductor pattern and extending on the upper major surface of the second insulator layer from a first part thereof located above the emitter region to a second part thereof located above the isolation region, passing over a part of the collector region, said fourth conductor pattern forming a parasitic MOS transistor in a part of the device region located under the fourth conductor pattern and defined between the emitter region and said part of the collector region located under the fourth conductor pattern, and another parasitic MOS transistor in a part of the device region located under the fourth conductor pattern and defined between said part of the collector region under the fourth conductor pattern and the isolation region also located under the fourth conductor pattern;
• said second conductor pattern extending on the upper major surface of the first insulator layer at least over a part of the device region wherein the parasitic MOS transistors are formed;
• and
• means for applying a predetermined voltage to said second conductor pattern, said predetermined voltage being chosen such that a turning-on of the parasitic MOS transistors is eliminated;
• said second conductor pattern and said third conductor pattern being connected with each other to form a common conductor pattern.