Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices

A gated thyristor formed at a face of a semiconductor layer of a first conductivity type, comprising:

• a first tank formed at a face to be of said second conductivity type opposite said first conductivity type;
• a second tank formed at said face to be of said first conductivity type and within said first tank;
• a first highly doped region formed at said face within said second tank to be of said second conductivity type;
• a second highly doped region formed at said face adjoining said first and said second tanks and to be of said first conductivity type;
• a third highly doped region formed at said face to be of said first conductivity type, a channel subregion of said first tank spacing said second highly doped region from said third highly doped region, said third highly doped region formed within said first tank and spaced from said second tank;
• a conductive gate insulatively disposed adjacent said channel subregion so as to control the conductance thereof, said third highly doped region and said conductive gate conductively coupled together;
• a fourth highly doped region of said second conductivity type formed at said face at a margin of said first tank and a portion of said semiconductor layer outside of said first tank;
• a fifth highly doped region of said second conductivity type formed at said face and spaced from said first tank, a second channel subregion of said semiconductor layer spacing said fourth region from said fifth region, a second conductive gate insulatively disposed adjcaent said second channel subregion;
• a sixth highly doped subregion of said second conductivity type formed at said face of said semiconductor layer, a third channel subregion of said semoconductor layer spacing said sixth region from said fifth region, said sixth region spaced from said fourth region and from said first tank;
• a first conductive connection coupling together said fifth region and said first region, a second conductive connection coupling together said sixth region and said second region, a source of a first signal coupled to said third conductive gate to turn said thyristor on, a source of a second signal coupled to said second conductive gate to turn said thyristor off.

An automotive electrical system, comprising:

• a gated thyristor formed at a face of a semiconductor layer of a first conductivity type, said semiconductor layer forming a portion of a monolithic integrated circuit chip, said thyristor including:
• a first tank formed at said face to be of said second conductivity type;
• a second tank formed at said face to be of said first conductivity type and within said first tank;
• a first highly doped region formed at said face within said second tank to be of said second conductivity type;
• a second highly doped region formed at said face adjoining said first and said second tanks and to be of said first conductivity type;
• a third highly doped region formed at said face to be of said first conductivity type, a channel subregion of said first tank spacing said second highly doped region from said third highly doped region, said third highly doped region formed within said first tank and spaced from said second tank;
• a conductive gate insulatively disposed adjacent said channel subregion so as to control the conductance thereof, said third highly doped region and said conductive gate conductively coupled together;
• a fourth highly doped region of said second conductivity type formed at said face at a margin of said first tank and a portion of said semiconductor layer outside of said first tank;
• a fifth highly doped region of said second conductivity type formed at said face and spaced from said first tank, a second channel subregion of said semiconductor layer spacing said fourth region from said fifth region, a second conductive gate insulatively disposed adjacent said second channel subregion;
• a sixth highly doped subregion of said second conductivity type formed at said face of said semiconductor layer, a third channel subregion of said semiconductor layer spacing said sixth region from said fifth region, said sixth region spaced from said fourth region and from said first tank;
• a first conductive connection coupling together said fifth region and said first region, a second conductive connection coupling together said sixth region and said second region;
• logic circuitry formed on said chip to generate first and second control signals, a source of said first control signal coupled to said third conductive gate to turn said thyristor on, a source of second control signal coupled to said second conductive gate to turn said thyristor off;
• and
• a peripheral electrical device coupled to said third region for sinking operating current thereto, a battery coupled to said peripheral electrical device for supplying said operating current, a ground terminal coupled to said first highly doped region.

A gated thyristor formed at a face of a semiconductor layer of a conductivity type, comprising:

• a first tank region having a second conductivity type opposite said first conductivity type;
• an annular second tank region of said first conductivity type formed at said face to laterally surround said first tank region;
• a third highly doped region of said first conductivity type formed within said first tank region near said second annular tank region;
• a fourth highly doped region of said second conductivity type formed within said third highly doped region;
• fifth, sixth, seventh and eighth highly doped regions formed to be of said second conductivity type in said semiconductor layer and spaced from said first and second tank regions, a first channel subregion of said semiconductor layer spacing said fifth and sixth highly doped regions, a first conductive gate insulatively disposed adjacent said first channel subregion, a second channel subregion of said semiconductor layer spacing said seventh and eight highly doped regions, a second conductive gate insulatively disposed adjaent said second channel subregion, said fifth and sixth highly doped regions spaced from said seventh and eighth highly doped regions;
• a first conductive connection coupling said fifth region with said first tank region, first and second voltage supplies, said first voltage supply supplying a voltage substantially different from that supplied by said second voltage supply, a second conductive connection coupling together said sixth region, said fourth region and said second voltage supply;
• a third conductive connection coupling said seventh region with said first tank;
• and
• a fourth conductive connection coupling said first voltage supply, said eighth region and said second annular tank region.