Method of making SRAM cell and structure with polycrystalline p-channel load devices

A method of producing a SRAM structure with polycrystalline P-channel load devices of an integrated circuit comprising:

• forming a field oxide region over a portion of a substrate;
• forming a first gate electrode of a first N-channel field effect device over the substrate having a source/drain region in the substrate and forming a second gate electrode of a second N-channel field effect device over a portion of the field oxide region and the substrate;
• forming a first insulating layer over the first and second N-channel devices and a portion of the substrate;
• patterning and etching the first insulating layer to expose a portion of the source/drain region of the first N-channel field effect device and a portion of the second gate electrode of the second N-channel field effect device;
• forming an interconnect layer containing both a doped polysilicon layer and a barrier layer over a portion of the first insulating layer, second gate electrode and source/drain region of the first N-channel device;
• patterning and etching the interconnect layer to define a shared contact region covering the exposed source/drain region of the first N-channel field effect device and the second gate electrode of the second N-channel field effect device;
• forming a second insulating layer over the first insulating layer and the interconnect layer;
• patterning and etching the second insulating layer to expose a portion of the interconnect layer;
• forming a first conductive layer of the second insulating layer and the interconnect layer;
• patterning and etching the first conductive layer to define a firs gate electrode of a first P-channel field effect device and a second gate electrode of a second P-channel device;
• forming a gate oxide layer over a portion of the first gate electrode of the first P-channel field effect device and a portion of the second gate electrode of the second P-channel field effect device exposing a portion of the second gate electrode;
• forming a second conductive layer over a portion of the first and second P-channel devices;
• and,
• patterning and etching the second conductive layer to define a source/drain and channel region of the first gate electrode of the first P-channel field effect device and disposed over the exposed portion of the first conductive layer.