Contact sidewall tapering with argon sputtering

A method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less comprising:

• providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover;
• forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said contact openings are desired;
• isotropic etching through a thickness portion of said multilayer insulating layer;
• anisotropic etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said contact opening;
• removing the said resist layer;
• subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said multilayer layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 30 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising:

• forming a resist masking layer over the said silicate glass layer having openings therein in the areas where the said contact openings are desired;
• isotropic etching through a thickness portion of said silicate glass layer;
• anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings;
• removing the said resist layer;
• and subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 60 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising:

• forming a resist masking layer over the said silicate glass layer having openings therein in the area where the said contact openings are desired;
• isotropic etching through a thickness portion of said silicate glass layer;
• anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings;
• removing the said resist layer;
• and subjecting the structure to an Argon sputter etching ambient that is influenced by a magnetic field that causes preferential etch in a direction approximately 45 degrees to the horizontal plane, to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began.