Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorMakio Uchida
Life of this patent
Estimating the term…
Abstract
A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken, the circuit blocks formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.
Claims15
A semiconductor integrated circuit device comprising:
- a logic circuit;
- and
- a memory coupled to said logic circuit for storing data, said memory including a word line, a plurality of sub-word lines each of which has first and second ends and a connecting portion at which a sub-word line is coupled to said word line with said plurality of sub-word lines substantially concurrently receiving a signal from said word line, a plurality of memory cell blocks each respectively coupled to a different one of said plurality of sub-word lines with each of said plurality of memory cell blocks including memory cells coupled between said first end and said connecting portion of the sub-word line and memory cells coupled between said second end and said connection portion of the sub-word line, a plurality of data lines which are coupled to said memory cells, and selection generator for generating and applying said signal to said word line.
A single chip semiconductor integrated circuit device comprising:
- external terminals;
- a logic circuit, coupled to said external terminals, and including an address generator for generating an address signal and data receiver for receiving data;
- and
- a memory coupled to said logic circuit for storing data, said memory including a plurality of sub-word lines each of which has first and second end portions and a connecting portion, a plurality of word lines each of which is coupled to a plurality of said plurality of sub-word lines at the connecting portions, a plurality of memory cells coupled between said first end portion and said connecting portion and memory cells coupled between said second end portion and said connecting portion with the sub-word lines coupled to a predetermined word line substantially concurrently receiving a signal from said predetermined word line, a plurality of data lines coupled to said memory cells, a signal generator, coupled to said plurality of word lines and to said address generator, for generating a signal to be applied to a word line according to said address signal, and a data output, coupled to said plurality of data lines and to said data receiver, for providing data stored in at least one of said memory cells to said data receiver.
Dependencies are inferred from the claim text.