Fully planar metalization process
AssigneeIntel Corporation
InventorsChiu H. Ting, Pei-Lin Pai
Life of this patent
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Abstract
A planar interconnect using selective, electroless deposition of a metal such as copper into interconnect channels is disclosed. A first dielectric layer is deposited on the surface of a substrate, such as an integrated circuit wafer. Thereafter, a second dielectric layer is formed on the first dielectric layer. Then a photoresist layer is spun on the top surface of the second dielectric layer. Channels are formed in the dielectric layers by patterning and etching the composite dielectric layers. Silicon atoms are implanted in the bottom of the interconnect channels and then the metal layer is selectively, electrolessly deposited to fill the channels in the first dielectric film, thus forming a level of interconnect. This process is repeated to form subsequent levels of interconnect.
Claims13
A method for forming a planar interconnect level for VLSI devices comprising:
- forming on a surface of a VLSI wafer a first dielectric layer having a planar top surface;
- forming a masking layer on said first dielectric layer;
- patterning said masking layer to define in said masking layer at least one location where an interconnect channel is to be formed;
- etching said first dielectric layer at said location through said patterned masking layer to form an interconnect channel in said first dielectric layer;
- implanting ions into the bottom surface of said interconnect channel, said ions forming a modified bottom surface of said interconnect channel to receive selective electroless metal deposition;
- removing said patterned masking layer;
- and
- depositing copper onto said modified bottom surface of said interconnect channel by selective electroless metal deposition, said deposition continuing until said interconnect channel is filled to a level substantially coincidence with the top surface of said first planar dielectric layer to thereby form a metal interconnect line, said metal interconnect line and said first dielectric layer forming a first planar interconnect level.
A method for forming a planar interconnect level for VLSI devices comprising:
- forming on a surface of a VLSI wafer a first dielectric layer having a planar top surface;
- forming a masking layer on said first dielectric layer;
- patterning said masking layer to define in said masking layer at least one location where an interconnect channel is to be formed;
- etching said first dielectric layer at said location through said patterned masking layer to form an interconnect channel in said first dielectric layer;
- implanting metal ions, selected from a group consisting of palladium, copper, gold, and silver, into the bottom surface of said interconnect channel, said metal ions forming a modified bottom surface of said interconnect channel to receive selective electroless metal deposition;
- removing said patterned masking layer;
- and
- depositing copper onto said modified bottom surface of said interconnect channel by selective electroless metal deposition, said deposition continuing until said interconnect channel is filled to a level substantially coincidence with the top surface of said first planar dielectric layer to thereby form a metal interconnect line, said metal interconnect line and said first dielectric layer forming a first planar interconnect level.
Dependencies are inferred from the claim text.