Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate

An integrated circuit device comprising:

• a N-type semiconductor substrate;
• a first N-type epitaxial layer disposed over said semiconductor substrate;
• a second P-type epitaxial layer disposed over said first epitaxial layer;
• a third N-type epitaxial layer disposed over said second epitaxial layer, said third epitaxial layer having first, second, and third tank regions for formation of a bipolar transistor, a N-channel MOSFET and a P-channel MOSFET;
• first and second P-type isolation regions for isolating said first epitaxial tank from said second and third tank regions;
• a first P-type buried ground region and extending through the first and second epitaxial layers disposed between said semiconductor substrate and said third epitaxial layer of said first tank region;
• first, second, third and fourth P-type diffusion regions formed in said first tank region, said first and second P-type diffusions being disposed in said first set of isolation regions for providing respective first and second collector regions for said bipolar transistor, said third and fourth diffusions being disposed in said epitaxial layer for providing emitter regions for said bipolar transistor;
• a fifth P-type diffusion disposed in said second tank region for providing a P-well for said N-channel MOSFET;
• sixth and seventh P-type diffusions disposed in said third tank region for providing source and drain regions for said P-channel MOSFET;
• a first N-type diffusion region formed in said first tank region between said third and fourth P-type diffusions for providing a base region for said bipolar transistor;
• second and third N-type diffusions formed in said second tank region for providing source and drain regions for said N-channel MOSFET.