Complementary semiconductor device having improved device isolating region
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakahisa Eimori, Wataru Wakamiya, Hiroji Ozaki, Yoshinori Tanaka, Shinichi Satoh
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakahisa Eimori, Wataru Wakamiya, Hiroji Ozaki, Yoshinori Tanaka, Shinichi Satoh
Estimating the term…
A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
A complementary semiconductor device comprising a first region of a first conductivity type formed on a main surface of a substrate of said first conductivity type and a second region of a second conductivity type different from said first conductivity type formed adjacent said first region, said complementary semiconductor device comprising:
A complementary semiconductor device in accordance with claim 23, wherein said complementary semiconductor device further comprises a fifth region of the first conductivity type formed between said third region and said second region on the main surface of said substrate and a sixth region of the second conductivity type formed between said first region and said fourth region on the main surface of said substrate.
A complementary semiconductor device comprising a first region of a first conductivity type formed on a main surface of a substrate of said first conductivity type and a second region of a second conductivity type different from said first conductivity type formed adjacent said first region, said complementary semiconductor device comprising:
A complementary semiconductor device comprising a first region of a first conductivity type formed on a main surface of a substrate of said first conductivity type and a second region of a second conductivity type different from said first conductivity type formed adjacent said first region, said complementary semiconductor device comprising:
A complementary semiconductor device comprising a first region of a first conductivity type formed on a main surface of a substrate of said first conductivity type and a second region of a second conductivity type different from said first conductivity type formed adjacent said first region, said complementary semiconductor device comprising:
A complementary semiconductor device comprising a first region of a first conductivity type formed on a main surface of a substrate of said first conductivity type and a second region of a second conductivity type different from said first conductivity type formed adjacent said first region, said complementary semiconductor device comprising:
Dependencies are inferred from the claim text.