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US 5,181,088 AGranted
Vertical field effect transistor with an extended polysilicon channel region
AssigneeKabushiki Kaisha Toshiba
InventorsYuuichi Mikata, Toshiro Usami
Life of this patent
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Abstract
An MOS FET of the semiconductor device includes a semiconductor substrate on which a projection is formed via a given film. The projection is made of a polysilicon having grain boundaries. A pair of gate electrodes are provided so that one of the gate electrodes faces the other thereof via side walls of the projection and gate oxide films. A conductive channel forming area is formed at the side walls of the projection, so that the extending direction of the channel is parallel to the thickness direction of the substrate.
Claims4
A semiconductor device having an MOS transistor structure, comprising:
- a projection formed of polysilicon having grain boundaries, said projection being over a main horizontal plane of a substrate;
- a film interposed between said projection and said substrate, said projection having two vertical side walls and said film having two vertical side walls each in alignment with respective ones of said vertical side walls of said projection to form first and second vertical side walls each comprising one of said vertical side walls of the projection and the aligned vertical side wall of the film;
- a first gate electrode which faces one of the vertical side walls of said projection, so that a conductive channel forming area is formed in said projection;
- a gate insulating film interposed between said first gate and said projection;
- a second gate electrode which faces the other vertical side wall of said projection, so that a conductive channel forming area is formed in said projection;
- a gate insulating film interposed between said second gate and said projection;
- a first region of a first conductivity type having a vertical side wall, said first region being on the main horizontal plane of said substrate with the vertical side wall of the first region coincident with a portion of the first vertical side wall;
- and
- a second region of the first conductivity type having a vertical side wall, the second region being on the main horizontal plane of said substrate with the vertical side wall of the second region coincident with a portion of the second vertical side wall.
6 more elements
A MOS transistor device comprising:
- a semiconductor substrate;
- a region of a first conductivity type over a surface of the substrate, the longitudinal direction of said region arranged substantially parallel to the surface of said substrate;
- a pair of gate electrodes each arranged substantially perpendicular to the surface of said substrate;
- a projection of a second conductivity type over the surface of said substrate, such that said projection is sandwiched by said gate electrodes, said projection having first and second end portions, the first end portion contacting said region along a line substantially perpendicular to the substrate;
- insulating films interposed between said gate electrodes and said projection;
- and
- another region of the first conductivity type on the second end portion of said projection.
4 more elements
A semiconductor device having an MOS transistor struture, comprising:
- a projection formed of a polysilicon layer having grain boundaries, said projection being over a main horizontal plane of a substrate, and said projection having first and second vertical side walls;
- a first gate electrode which faces one of the first vertical side wall of said projection, so that a conductive channel forming area is formed in said projection;
- a first gate insulating film interposed between said first gate and said projection;
- a second gate electrode which faces the second vertical side wall of said projection, so that a conductive channel forming area is formed in said projection;
- a second gate insulating film interposed between said second gate and said projection;
- a first region of a first conductivity type having a vertical side wall, said first region being on the main horizontal plane of said substrate with the vertical side wall of the first region coincident with a portion of the first vertical side wall of said projection;
- and
- a second region of the first conductivity type having a vertical side wall, the second region being on the main horizontal plane of said substrate with the vertical side wall of the second region coincident with a portion of the second vertical side wall of said projection.
5 more elements
Dependencies are inferred from the claim text.