Tapered opening sidewall with multi-step etching process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Tsung Liu, Jin-Yuan Lee, Jiann-Kwang Wang, Chue-San Yoo, Pei-Jan Wang
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Tsung Liu, Jin-Yuan Lee, Jiann-Kwang Wang, Chue-San Yoo, Pei-Jan Wang
Estimating the term…
A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer. The remaining thickness of the multilayer insulating layer is anisotropically etched through to the semiconductor substrate to form the desirable tapered opening with a metal step coverage improvement over the state of the art between about 20 to 60%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in the contact hole to the metal thickness on the horizontal area. The resist layer mask is removed.
A method for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor comprising:
In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, a process for forming tapered contact openings to device elements comprising:
In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a composite layer composed of a silicon oxide layer, spin-on-glass and a silicon oxide layer, a process for forming tapered contact openings to device elements comprising:
Dependencies are inferred from the claim text.