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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsWataru Wakamiya, Yoshinori Tanaka, Takahisa Eimori, Hiroji Ozaki, Hiroshi Kimura, Shinichi Satoh
Estimating the term…
A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, comprising the steps of:
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, comprising the steps of:
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, comprising the steps of:
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, comprising the steps of:
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, comprising the steps of:
A manufacturing method of a semiconductor memory device including a memory cell having one access transistor and one capacitor, said method comprising the steps of:
Dependencies are inferred from the claim text.