Method of making high current, high voltage breakdown field effect transistor
AssigneeNorth Carolina State University
InventorsUmesh K. Mishra, Robert J. Trew
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AssigneeNorth Carolina State University
InventorsUmesh K. Mishra, Robert J. Trew
Estimating the term…
The gate voltage breakdown of an integrated circuit field effect transistor, expecially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resistivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.
A method of fabricating an integrated circuit compound semiconductor metal semiconductor field effect transistor (MESFET) comprising the steps of:
A method of fabricating an integrated circuit field effect transistor comprising the steps of:
Dependencies are inferred from the claim text.