Non-volatile semiconductor memory device with voltage stabilizing electrode

A programmable read-only memory comprising:

• a semiconductive substrate having a first surface area and a second surface area;
• parallel bit lines insulatively arranged above said substrate;
• a memory cell section arranged on said substrate and containing a NAND type cell unit associated with one of said bit lines,
• said NAND type cell unit being provided in said first surface area and having a series-connected circuit of a number of data storage transistors with control gate layers and a switching transistor;
• a conductive layer insulatively disposed above said substrate in the second surface area thereof, and positioned adjacent to said one of said bit lines, said conductive layer extending in parallel with said bit lines and being adapted to be coupled to a source voltage;
• and
• a heavily-doped semiconductor layer arranged in said substrate and having the same conductivity type as said substrate, for connecting said conductive layer to said substrate, and for suppressing said substrate from varying in potential by constantly applying the source voltage to said substrate while said memory operates in one of a write mode and an erase mode.

An electrically erasable and programmable semiconductor memory device comprising:

• a semiconductive support layer;
• parallel bit lines insulatively overlaying said support layer;
• parallel word lines insulatively crossing with said bit lines to provide cross points therebetween;
• a memory cell section containing an array of memory cells arranged at those of said crossing points which are associated with a certain one of said bit lines;
• switching transistor means for selectively connecting said array of memory cells to said certain one of said bit lines, said switching transistor means having double-layered conductive layers which extend in parallel with said word lines and which are electrically coupled together at a plurality of contact portions provided at a predetermined interval along said double-layered conductive layers;
• and
• a plurality of conductive layers which extend in parallel with said bit lines and each of which overlies a corresponding one of said plurality of contact portions, said conductive layers being coupled to said support layer.

An electrically erasable and programmable semiconductive memory device comprising:

• a semiconductive support layer;
• parallel bit lines insulatively overlying said support layer;
• parallel word lines insulatively crossing with said bit lines to provide crossing points therebetween;
• a memory cell section containing an array of memory cells arranged at those of said crossing points which are associated with a certain one of said bit lines;
• switching transistor means for selectively connecting said array of memory cells to said one of said bit lines, said switching transistor means having double-layered conductive layers which extend in parallel with said word lines and which are electrically coupled together at a plurality of contact portions provided at a predetermined interval along said double-layered conductive layers;
• and
• potential stabilizer means for stabilizing said support layer to be at a preselected constant voltage by applying the preselected constant voltage to said support layer, said potential stabilizer means comprising at least one conductive layer extending in parallel with said bit lines and overlying a corresponding one of said plurality of contact portions, said conductive layer being coupled to said support layer.