Arrangement of an integrated circuit on a circuit board

An arrangement of an integrated circuit chip on a multi-layered through-contacting circuit board substrate, including bonding-wires extending between chip contacts and substrate contacts, said substrate contacts being located within a narrow connector strip extending in parallel with the boundary of an integrated circuit chip mounting region on said circuit board substrate in approximately the same measurements and geometric sequence as the chip contacts are located on the circuit board substrate in a plane of a surface of the substrate, and thin conductive paths extending in said plane from the substrate contrast within san edge strip of the IC chip mounting region, said thin conductive paths extending and spreading apart in a fan-like manner from the substrate contacts to terminations of the thin conductive paths at end surfaces of vias in said circuit board substrate which have a substantially larger cross-sectional dimension than the width of the thin conductive paths, and larger cross-sectional vias being formed as a two dimensional array of vias in said circuit board substrate which are spaced apart in a relatively large two dimensional strip area located blow the integrated circuit chip.