Method for making buried isolation
AssigneeMotorola, Inc.
InventorsLisa K. Garling, Robert H. Reuss, Ping Wang
Life of this patent
Estimating the term…
Abstract
A method for making bipolar transistors with a first and a second buried collectors that are separated wherein the first and second buried collectors are separated by a p buried layer that is made by depositing a heavily doped boron layer and subsequently diffusing boron from the boron layer into the area between the first and second buried collector.
Claims10
A method for reducing punchthrough comprising:
- providing a p-type semiconductor substrate;
- providing a first buried collector region with a first junction and a second buried collector with a second junction, wherein the first and second junctions in the semiconductor substrate are positioned with a small region of the p-type semiconductor substrate between the first and second buried collectors;
- depositing a heavily doped layer of silicon on the semiconductor substrate, covering the region and the first and second buried collectors;
- depositing a lightly doped layer of epitaxial silicon over the heavily doped layer of epitaxial silicon;
- and
- completing subsequent thermal fabrication sequences for making at least a bipolar transistor which diffuses at least a portion of the dopant of the heavily doped layer into the region between the first and second buried collectors and into the first and second buried collector during subsequent thermal processing making a doped isolation barrier between the first buried collector and the second buried collector, thereby positioning a more heavily doped dopant barrier between the first and second buried collector thus reducing punchthrough.
A method for making bipolar transistors with a first and a second buried collector that are separated, wherein the first and second buried collectors are spaced apart by a p buried layer that is made by depositing a heavily doped boron layer onto the first and second buried collectors, as well as a space apart between the first and second buried collectors and subsequently diffusing boron from the doped boron layer into the space apart by growing a subsequent epi layer and by subsequent processing steps on the epi layer, thereby creating the p buried layer.
A method for reducing relative capacitance for a bipolar transistor comprising:
- providing a p-type semiconductor substrate;
- providing a first n+ buried collector and a second n+buried collector, wherein the first n+ buried collector and the second n+ buried collector are positioned in the p-type semiconductor substrate, with a small region positioned in the p-type substrate between the first n+ buried collector and the second n+ buried collector;
- depositing a heavily doped p-type epitaxial layer covering at least the region between the first and second n+ buried collectors;
- and
- having at least a portion of the dopant from the heavily doped epitaxial layer move into at least the region between the first and second n+ buried collectors during subsequent thermal processing, thereby reducing capacitance between the first and second n+ buried collectors and the p-type substrate.
Dependencies are inferred from the claim text.