Frequency divider employing multiple stages of master/slave flip-flops

A frequency divider comprising:

• at least three master-slave flip-flops in at least first, second, and third stages, each stage including a master flip-flop and a slave flip-flop to construct a 1/5 frequency divider;
• a first AND circuit to which inverted outputs from the master flip-flops of the first and second stages are input;
• a second AND circuit to which an output from the slave flip-flop of the second stage and an inverted output from the slave flip-flop of the third stage are input;
• and
• an OR circuit to which outputs of said first and second AND circuits are input and from which a 1/2.5 divided output is obtained.

A frequency divider comprising:

• at least three master-slave flip-flops in at least first, second, and third stages, each stage including a master flip-flop and a slave flip-flop to construct a 1/5 frequency divider;
• a first AND circuit to which outputs from the slave flip-flops of the first and third stages are input;
• a second AND circuit to which an output from the master flip-flop of the first stage and an inverted output from the master flip-flop of the second stage are input;
• and
• an OR circuit to which outputs of said first and second AND circuits are input and from which a 1/2.5 divided output is obtained.

A frequency divider comprising:

• at least three master-slave flip-flops in at least first, second, and third stages, each stage including a master flip-flop and a slave flip-flop to construct a 1/6 frequency divider;
• a NOR circuit to which an output from the slave flip-flop of the first stage and from the master flip-flop of the third stage are input;
• an AND circuit to which an output from the slave flip-flop of the first stage and an output from the master flip-flop of the third stage are input;
• and
• an OR circuit to which outputs from said NOR circuit and said AND circuit are input and from which a 1/3 divided output is obtained.

A frequency divider comprising:

• four master-slave flip-flops connected to each other in first, second, third, and fourth stages, each stage including a master and a slave flip-flop to construct a 1/7 frequency divider;
• a first OR circuit to which outputs from the master flip-flop of the first stage and from the slave flip-flop of the second stage are input;
• a second OR circuit to which an inverted output from the master flip-flop of the third stage and an output from the slave flip-flop of the fourth stage are input;
• and
• an AND circuit to which outputs of said first and second OR circuits are input and from which a 1/3.5 divided output is obtained.

A frequency divider comprising:

• three master-slave flip-flops in at least first, second, and third stages, each stage including a master flip-flop and a slave flip-flop to construct a 1/5 frequency divider;
• a first AND circuit to which inverted outputs from the master flip-flops of the first and second stages are input;
• a second AND circuit to which an output from the slave flip-flop of the second stage and an inverted output from the slave flip-flop of the third stage are input;
• a third AND circuit to which an output from the master flip-flop of the first stage and an output from the slave flip-flop of the second stage are input;
• a fourth AND circuit to which an inverted output from the slave flip-flop of the first stage and an inverted output from the master flip-flop of the second stage are input;
• an OR circuit to which outputs of said first and second AND circuits are input;
• a NOR circuit to which outputs from said third and fourth AND circuits are input;
• and
• a differential amplifier to which outputs of said OR circuit and said NOR circuit are input and from which a 1/2.5 divided output whose pulse width is 1/2 of its period is obtained.