Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:

• a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
• b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
• c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
• d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
• e) removing said second insulating layer until upper portion of said first conductive layer is exposed;
• f) removing said exposed first conductive upper layer until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said container storage capacitors having inner and outer walls;
• g) simultaneously removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
• h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said capacitor and said partially remaining first insulating layer;
• and
• i) forming a second conductive layer superjacent and coextensive said third insulating layer.