Programmable delay circuit having a buffer stage connected in cascode between the outputs of a plurality of differential amplifiers and the output terminal

Abstract

A programmable delay circuit of the present invention is comprised of an input terminal to which an input signal to be delayed is supplied, N (N.gtoreq.2) delay circuits of a plurality of stages connected in cascade, a plurality of differential amplifier transistors connected to respective stages between the delay circuits of the plurality of stages and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to the pair of differential amplifier transistors, a common output terminal commonly connected to respective outputs of a pair of differential amplifier transistors of the plurality of differential amplifiers and a control circuit for selectively controlling the current switches of the plurality of differential amplifiers, wherein even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced. When a buffer stage connected in cascode is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed.

Dependencies are inferred from the claim text.