Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact

Abstract

An improved DRAM cell having a tantalum metal lower plate, a tantalum-silicide buried contact, and a tantalum oxide capacitor dielectric layer is disclosed. Also disclosed are several methods for fabricating the improved cell. Fabrication of an array of the improved cells proceeds through the storage-node contact opening stage in a manner consistent with the fabrication process utilized for conventional stacked-cell DRAM arrays. The process for fabricating the improved cells deviates from convention after storage-node contact openings are formed. A tantalum metal layer is conformally deposited over the wafer surface, patterned and etched to create individual storage-node plates. The wafer is then subjected to an elevated temperature step in an oxygen ambient, which creates both a tantalum silicide layer at the tantalum-silicon interface of each storage-node contact, and a tantalum oxide dielectric layer on the exposed surfaces of each storage-node plate. The tantalum oxide layer then annealed in order to reduce its leakage current characteristics. Following the annealing step, a thin barrier layer of a material such as silicon nitride is blanket deposited. This is followed by the deposition of a polysilicon cell plate layer.

Dependencies are inferred from the claim text.