Scannable latch system and method

A combination clock driver and scannable latch to facilitate at-speed testing of integrated circuits, said combination comprising:

• a master latch having a data input, scan input, control inputs and a first and a second outputs, the data input and the scan input coupled to receive data and the control inputs coupled to receive master control signals, the master latch selecting data from one of the scan input and the data input and holding the selected data at the first output in a stable state in response to the master control signals;
• a slave latch having a data input, a control input and an output, the data input coupled to the first output of the master latch and the control input coupled to receive a slave control signal the slave latch holding the data at the output in a stable state in response to the slave control signal;
• an auxiliary latch having a data input, a control input and an output, the data input coupled to the second output of the master latch and the control input coupled to receive an auxiliary control signal, the auxiliary latch receiving and storing data from the second output of the master latch in response to the auxiliary control signals;
• and
• clock driver circuit having inputs coupled to receive a clock signal and a control signal for producing the master control signals and the slave control signals, said clock driver circuit having first and second outputs for sending the master control signals coupled to the control inputs of the master latch for selecting the input to the master latch and latching the master latch, and a third output for sending the slave control signal coupled to the control input of the slave latch for latching the slave latch.