Pulse phase difference encoding circuit

A pulse phase difference encoding circuit for between first pulse and a second pulse, comprising:

• a delayed pulse generating means having a plurality of delay elements connected in series to form a series circuit, one end of the series circuit receiving the first pulse, for generating a plurality of delayed pulses while the first pulse is passing through the delay elements;
• a position signal generating means for selecting a latest one of the delayed pulses upon receiving the second pulse certain time after the first pulse, and generating a positional signal indicating a position of the selected delayed pulse among the other non-selected delayed pulses;
• output means for receiving the positional signal and producing a digital signal indicating a time period between a time of input of the first pulse and a time of input of the second pulse;
• means for connecting one end of the series circuit to the other end thereof to repeatedly circulate the first pulse from the one end toward the other end through the delay elements of the series circuit;
• counting means for counting the number of rounds of circulation of the first pulse in the series circuit;
• and
• means for supplementing the digital signal provided by the output means with the number of rounds of circulation counted by the counting means, thereby having the digital signal indicate the phase difference between the first and second pulses.

A phase difference encoding circuit for converting a phase difference between a first pulse generated at optional timing and a second pulse generated after the first pulse, into a digital signal, comprising:

• a delayed pulse generating ring circuit having a plurality of series-connected inverters to which the first pulse is applied and through which the first pulse is continuously passed, intermediate points between the inverters repeatedly generating a plurality of delayed pulses in response to the passage of the first pulse, the last inverter being connected to the first inverter to circulate the first pulse in the delayed pulse generating ring circuit;
• a pulse selector having a plurality of flip-flops for receiving the delayed pulses respectively from the delayed pulse generating ring circuit as well as the second pulse as a clock signal, the flip-flops storing and providing statuses of the delayed pulses when the second pulse occurs, the pulse selector further having logic circuits connected to the flip-flops to provide a positional signal indicating a position of the first pulse in the inverters;
• an encoder for receiving outputs of the logic circuits of the pulse selector and providing a first digital signal representing predetermined digits corresponding to the positional signal;
• a first counter connected to a first output point located at the middle of the series-connected inverters of the delayed pulse generating ring circuit, for receiving a count signal whenever the first pulse passes through the first output point, counting the first number of rounds of circulation of the first pulse, and providing a result of the counting;
• a second counter connected to a second output point located at an output of the last inverter of the series-connected inverters of the delayed pulse generating ring circuit, receiving a count signal whenever the first pulse passes through the second output point, counting the second number of rounds of circulation of the first pulse, and providing a result of the counting;
• a first flip-flop for receiving and providing an output of the first counter;
• a second flip-flop for receiving and providing an output of the second counter;
• a multiplexer for receiving an output of the encoder, and selectively providing one of outputs of the first and second flip-flops according to the output of the encoder;
• and
• an output flip-flop for receiving the output of the encoder as predetermined bits, as well as an output of the multiplexer as higher bits consecutive to the predetermined bits, and combining the bits to form the digital signal indicating the phase difference between the first and second pulses.